Course curriculum

  • 1
    Getting Started
    • Introduction
  • 2
    Introduction
    • MCU Introduction
    • CPU Overview
    • Instruction Pipeline
    • System Bus
  • 3
    microAptive®/M5150 Core ISA
    • Overview
    • CPU Registers
    • Shadow Registers
    • Addressing Modes
    • Instruction Categories
    • Data Types
    • Endianness
    • Coprocessors
  • 4
    Memory Organization
    • Overview
    • Modes of Operation
    • Virtual Address Space
    • Virtual vs. Physical Memory
    • Address Translation
    • Memory Map Example
    • Alignment
    • Level 1 Cache
    • Prefetch Module
  • 5
    L1 Cache
    • What is Cache Memory ?
    • How Does Cache Work ?
    • Cache Coherency Defined
    • Managing Cache Coherency
    • Cache Policy Comparison Chart
    • Changing The Cache Policy
    • Cache Management Assembly Instructions
    • Completely Disable the Cache
    • Disable Cache for Shared Data
    • Maintaining Cache Coherency (SUMMARY)
  • 6
    Exception Mechanism
    • PIC32MZ Exception Overview
    • Exception Types
    • Entry Points
    • Control Registers
    • Operation
    • Interrupt & Exception Usage
    • Processor Initialization
  • 7
    Project 1: Interrupt Code Example (in C)
    • Objective
    • Hardware Tools
    • Software Tools & Exercise Files
    • Procedure
    • Results
    • Conclusions
  • 8
    Project 2: General Exception Code Example (in C)
    • Objective
    • Hardware Tools
    • Software Tools & Exercise Files
    • Procedure
    • Results
    • Conclusions